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  the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. mos integrated circuit pd4516421a, 4516821a, 4516161a for rev.p 16m-bit synchronous dram 2-banks , lvttl data sheet document no. e0122n10 (ver.1.0) (previous no. m12939ej3v0ds00) date published may 2001 cp (k) printed in japan elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. description the pd4516421a, 4516821a, 4516161a are high-speed 16,777,216-bit synchronous dynamic random-access memories, organized as 2,097,152 4 2, 1,048,576 8 2, 524,288 16 2 (word bit bank), respectively. the synchronous drams achieved high-speed data transfer using the pipeline architecture. all inputs and outputs are synchronized with the positive edge of the clock. the synchronous drams are compatible with low voltage ttl (lvttl). these products are packaged in 44-pin tsop (ii) ( 4, 8) and 50-pin tsop (ii) ( 16). features ? fully synchronous dynamic ram, with all signals referenced to a positive clock edge ? pulsed interface ? possible to assert random column address in every cycle ? dual internal banks controlled by a11(bank select) ? byte control ( 16) by ldqm and udqm ? programmable wrap sequence (sequential / interleave) ? programmable burst length (1, 2, 4, 8 and full page) ? programmable /cas latency (2 and 3) ? automatic precharge and controlled precharge ? cbr (auto) refresh and self refresh ? 4, 8, 16 organization ? single 3.3 v 0.3 v power supply ? lvttl compatible inputs and outputs ? 2,048 refresh cycles / 32 ms ? burst termination by burst stop command and precharge command 

data sheet e0122n10 2 pd4516421a, 4516821a, 4516161a for rev.p ordering information part number organization (word bit bank) clock frequency mhz (max.) package pd4516421ag5-a80-9nf 2m 4 2 125 44-pin plastic tsop (ii) pd4516421ag5-a10-9nf 100 (10.16mm (400)) pd4516421ag5-a10b-9nf 100 pd4516421ag5-a12-9nf 83 pd4516821ag5-a80-9nf 1m 8 2 125 44-pin plastic tsop (ii) pd4516821ag5-a10-9nf 100 (10.16mm (400)) pd4516821ag5-a10b-9nf 100 pd4516821ag5-a12-9nf 83 pd4516161ag5-a80-9nf 512k 16 2 125 50-pin plastic tsop (ii) pd4516161ag5-a10-9nf 100 (10.16mm (400)) pd4516161ag5-a10b-9nf 100 pd4516161ag5-a12-9nf 83 pd4516421ag5-a80l-9nf 2m 4 2 125 44-pin plastic tsop (ii) pd4516421ag5-a10l-9nf 100 (10.16mm (400)) pd4516421ag5-a10bl-9nf 100 pd4516421ag5-a12l-9nf 83 pd4516821ag5-a80l-9nf 1m 8 2 125 44-pin plastic tsop (ii) pd4516821ag5-a10l-9nf 100 (10.16mm (400)) pd4516821ag5-a10bl-9nf 100 pd4516821ag5-a12l-9nf 83 pd4516161ag5-a80l-9nf 512k 16 2 125 50-pin plastic tsop (ii) pd4516161ag5-a10l-9nf 100 (10.16mm (400)) pd4516161ag5-a10bl-9nf 100 pd4516161ag5-a12l-9nf 83 

data sheet e0122n10 3 pd4516421a, 4516821a, 4516161a for rev.p part number pd4516821ag5 - a10l 161 [ x4, x8 ] [ x16 ] organization interface number of banks organization memory density synchronous dram number of banks & interface package low voltage minimum cycle time low power 16 : x16 1 : lvttl r note ( 1 : 1bank) 4 : x4 8 : x8 16 : 16m bits 1 : 2bank, lvttl g5 : tsop(ii) a : 3.3 0.3 v 80 : 8 ns (125 mhz) 10 : 10 ns (100 mhz) 12 : 12 ns (83 mhz) 2 : 2bank version 

data sheet e0122n10 4 pd4516421a, 4516821a, 4516161a for rev.p pin configurations /xxx indicates active low si gnal. [ pd4516421a] 44-pin plastic tsop (ii) (10.16mm (400)) 2m words 4 bits 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v cc nc v ss q dq0 v cc q nc v ss q dq1 v cc q nc nc /we /cas /ras /cs a11 a10 a0 a1 a2 a3 v cc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 v ss nc v ss q dq3 v cc q nc v ss q dq2 v cc q nc nc dqm clk cke nc a9 a8 a7 a6 a5 a4 v ss a0 to a11 note : address inputs dq0 to dq3 : data inputs / outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dqm : dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a10 : row address inputs a0 to a9 : column address inputs a11 : bank select 

data sheet e0122n10 5 pd4516421a, 4516821a, 4516161a for rev.p [ pd4516821a] 44-pin plastic tsop (ii) (10.16mm (400)) 1m words 8 bits 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v cc dq0 v ss q dq1 v cc q dq2 v ss q dq3 v cc q nc nc /we /cas /ras /cs a11 a10 a0 a1 a2 a3 v cc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 v ss dq7 v ss q dq6 v cc q dq5 v ss q dq4 v cc q nc nc dqm clk cke nc a9 a8 a7 a6 a5 a4 v ss a0 to a11 note : address inputs dq0 to dq7 : data inputs / outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dqm : dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a10 : row address inputs a0 to a8 : column address inputs a11 : bank select 

data sheet e0122n10 6 pd4516421a, 4516821a, 4516161a for rev.p [ pd4516161a] 50-pin plastic tsop (ii) (10.16mm (400)) 512k words 16 bits 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 v cc dq0 dq1 v ss q dq2 dq3 v cc q dq4 dq5 v ss q dq6 dq7 v cc q ldqm /we /cas /ras /cs a11 a10 a0 a1 a2 a3 v cc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v ss dq15 dq14 v ss q dq13 dq12 v cc q dq11 dq10 v ss q dq9 dq8 v cc q nc udqm clk cke nc a9 a8 a7 a6 a5 a4 v ss a0 to a11 note : address inputs dq0 to dq15 : data inputs / outputs clk : clock input cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable ldqm : lower dq mask enable udqm : upper dq mask enable v cc : supply voltage v ss : ground v cc q : supply voltage for dq v ss q : ground for dq nc : no connection note a0 to a10 : row address inputs a0 to a7 : column address inputs a11 : bank select 

data sheet e0122n10 7 pd4516421a, 4516821a, 4516161a for rev.p block diagram clock generator mode register command decoder control logic row address buffer & refresh counter column address buffer & burst counter data control circuit latch circuit input & output buffer sense amplifier column decoder & latch circuit bank b bank a row decoder dq dqm clk cke address /cs /ras /cas /we 

data sheet e0122n10 8 pd4516421a, 4516821a, 4516161a for rev.p contents 1. input / output pin function ................................................................................................. ........... 10 2. commands .................................................................................................................... ................... 11 3. simplified state diagram .................................................................................................... ............. 14 4. truth table ................................................................................................................. ...................... 15 4.1 command truth table......................................................................................................... .................... 15 4.2 dqm truth table ............................................................................................................. ......................... 15 4.3 cke truth table............................................................................................................. .......................... 15 4.4 operative command table .................................................................................................... ................ 16 4.5 command truth table for cke ................................................................................................ .............. 19 4.6 command truth table for two banks operation ................................................................................ 20 5. initialization .............................................................................................................. ........................ 22 6. programming the mode register ............................................................................................... .... 23 7. mode register ............................................................................................................... ................... 24 7.1 burst length and sequence .................................................................................................. ................ 25 8. address bits of bank-select and precharge ................................................................................. 2 6 9. precharge ................................................................................................................... ....................... 27 10. auto precharge ............................................................................................................. ................... 28 10.1 read with auto precharge .................................................................................................. ................ 28 10.2 write with auto precharge ................................................................................................. ................. 29 11. read / write command interval .............................................................................................. ........ 30 11.1 read to read command interval ............................................................................................. ........... 30 11.2 write to write command interval ........................................................................................... ............. 30 11.3 write to read command interval ............................................................................................ ............ 31 11.4 read to write command interval ............................................................................................ ............ 32 12. burst termination .......................................................................................................... .................. 33 12.1 burst stop command ........................................................................................................ .................. 33 12.2 precharge termination ..................................................................................................... ................... 34 12.2.1 precharge termination in read cycle .................................................................................... 34 12.2.2 precharge termination in write cycle .................................................................................. 3 5 

data sheet e0122n10 9 pd4516421a, 4516821a, 4516161a for rev.p 13. electrical specifications .................................................................................................. ................ 36 13.1 ac parameters for read timing ............................................................................................. ............ 42 13.2 ac parameters for write timing ............................................................................................ ............. 43 13.3 relationship between frequency and latency ................................................................................ . 44 13.4 mode register set ......................................................................................................... ....................... 45 13.5 power on sequence and cbr (auto) refresh .................................................................................. . 46 13.6 /cs function .............................................................................................................. ........................... 47 13.7 clock suspension during burst read (using cke function) .......................................................... 48 13.8 clock suspension during burst write (using cke function) .......................................................... 50 13.9 power down mode and clock mask ............................................................................................ ....... 52 13.10 cbr (auto) refresh ....................................................................................................... ....................... 53 13.11 self refresh (entry and exit) ............................................................................................ ................... 54 13.12 random column read (page with same bank) ................................................................................ 55 13.13 random column write (page with same bank) ................................................................................ 57 13.14 random row read (ping-pong banks) ........................................................................................ ..... 59 13.15 random row write (ping-pong banks) ....................................................................................... ...... 61 13.16 read and write ........................................................................................................... .......................... 63 13.17 interleaved column read cycle ............................................................................................ .............. 65 13.18 interleaved column write cycle ........................................................................................... .............. 67 13.19 auto precharge after read burst .......................................................................................... .............. 69 13.20 auto precharge after write burst ......................................................................................... .............. 71 13.21 full page read cycle ..................................................................................................... ...................... 73 13.22 full page write cycle .................................................................................................... ....................... 75 13.23 byte write operation ..................................................................................................... ....................... 77 13.24 burst read and single write (option) ..................................................................................... ........... 78 13.25 full page random column read ............................................................................................. ........... 79 13.26 full page random column write ............................................................................................ ........... 80 13.27 pre (precharge) termination of burst ..................................................................................... .......... 81 14. package drawings ........................................................................................................... ................ 83 15. recommended soldering condition ............................................................................................ .. 85 16. revision history ........................................................................................................... .................... 86 

data sheet e0122n10 10 pd4516421a, 4516821a, 4516161a for rev.p 1. input / output pin function pin name input / output function clk input clk is the master clock input. other inputs signals are referenced to the clk rising edge. cke input cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not issued and the pd4516 xxxa sus pends operation. when the pd4516 xxxa is not in burst m ode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. /cs input /cs low starts the command input cycle. when /cs is high, commands are ignored but operations continue. /ras, /cas, /we input /ras, /cas and /we have the same symbols on conventional dram but different functions. for details, refer to the command table. a0 - a10 input row address is determined by a0 - a10 at the clk (clock) rising edge in the active command cycle. it does not depend on the bit organization. column address is determined by a0 - a9 at the clk rising edge in the read or write command cycle. it depends on the bit organization: a0 - a9 for 4 device, a0 ? a8 for 8 device, a0 ? a7 for 16 device. a10 defines the precharge mode. when a10 is high in the precharge command cycle, both banks are precharged; when a10 is low, only the bank selected by a11 is precharged. when a10 is high in read or write command cycle, the precharge starts automatically after the burst access. a11 input a11 is the bank select signal. in command cycle, a11 low select bank a and a11 high high select bank b. dqm, udqm, ldqm input dqm controls i/o buffers. in 16 products, udqm and ldqm control upper byte and lower byte i/o buffers, respectively. in read mode, dqm controls the output buffers like a conventional /oe pin. dqm high and dqm low turn the output buffers off and on, respectively. the dqm latency for the read is two clo cks. in write mode, dqm controls the word mask. input data is written to the memory cell if dqm is low but not if dqm is high. the dqm latency for the write is zero. dq0 - dq15 input / output dq pins have the same function as i/o pins on a conventional dram. v cc , v ss , v cc q, v ss q (power supply) v cc and v ss are power supply pins for internal circuits. v cc q and v ss q are power supply pins for the output buffers. 

data sheet e0122n10 11 pd4516421a, 4516821a, 4516161a for rev.p 2. commands mode register set command (/cs, /ras, /cas, /we = low) the pd4516 xxxa has a m ode register that defines how the device operates. in this command, a0 through a11 are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when both banks are in idle state. during 2 clk (t rsc ) following this command, the pd4516 xxxa cannot accept any other commands. fig.1 mode register set command add a10 a11 /we /cas /ras /cs cke clk h activate command (/cs, /ras = low, /cas, /we = high) the pd4516 xxxa has two banks, each with 2,048 rows. this command activates the bank selected by bs(a11) and a row address selected by a0 through a10. this command corresponds to a conventional dram?s /ras falling. fig.2 row address strobe and bank activate command add a10 a11 /we /cas /ras /cs cke clk h row row (bank select) precharge command (/cs, /ras, /we = low, /cas = high) this command begins precharge operation of the bank selected by bs(a11). when a10 is high, both banks are precharged, regardless of bs(a11). when a10 is low, only the bank selected by bs(a11) is precharged. bs(a11) low selects bank a and bs(a11) high selects bank b. after this command, the pd4516 xxxa can?t accept the activate command to the precharging bank during t rp (precharge to activate command period). this command corresponds to a conventional dram?s /ras rising. fig.3 precharge command add a10 a11 /we /cas /ras /cs cke clk h (bank select) (precharge select) 

data sheet e0122n10 12 pd4516421a, 4516821a, 4516161a for rev.p write command (/cs, /cas, /we = low, /ras = high) if the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. the first write data in burst mode can input with this command with subsequent data on following clocks. fig.4 column address and write command add a10 a11 /we /cas /ras /cs cke clk h (bank select) col. read command (/cs, /cas = low, /ras, /we = high) read data is available after /cas latency requirements have been met. this command sets the burst start address given by the column address. fig.5 column address and read command add a10 a11 /we /cas /ras /cs cke clk h (bank select) col. cbr (auto) refresh command (/cs, /ras, /cas = low, /we, cke = high) this command is a request to begin the cbr (auto) refresh operation. the refresh address is generated internally. before executing cbr (auto) refresh, both banks must be precharged. after this cycle, both banks will be in the idle (precharged) state and ready for a row activate command. during t rc period (from refresh command to refresh or activate command), the pd4516 xxxa c annot accept any other command. fig.6 cbr (auto) refresh command add a10 a11 /we /cas /ras /cs cke clk h (bank select) 

data sheet e0122n10 13 pd4516421a, 4516821a, 4516161a for rev.p self refresh entry command (/cs, /ras, /cas, cke = low, /we = high) after the command execution, self refresh operation continues while cke remains low. when cke goes high, the pd4516 xxxa exits the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. before executing self refresh, both banks must be precharged. fig.7 self refresh entry command add a10 a11 /we /cas /ras /cs cke clk (bank select) burst stop command (/cs, /we = low, /ras, /cas = high) this command can stop the current burst operation. fig.8 burst stop command in full page mode add a10 a11 /we /cas /ras /cs cke clk (bank select) h no operation (/cs = low, /ras, /cas, /we = high) this command is not an execution command. no operations begin or terminate by this command. fig.9 no operation add a10 a11 /we /cas /ras /cs cke clk h (bank select) 

data sheet e0122n10 14 pd4516421a, 4516821a, 4516161a for rev.p 3. simplified state diagram 

data sheet e0122n10 15 pd4516421a, 4516821a, 4516161a for rev.p 4. truth table 4.1 command truth table function symbol cke /cs /ras /cas /we a11 a10 a9 - a0 n ? 1 n device deselect desl h h no operation nop h lhhh burst stop bst h lhhl read read h lhlhvlv read with auto precharge reada h lhlhvhv write writ h lhl lvlv write with auto precharge writa h lhl lvhv bank activate act h llhhvvv precharge select bank pre h llhlvl precharge both banks pall h llhl h mode register set mrs h llllllv remark h = high level, l = low level, = high or low level (don't care), v = valid data input 4.2 dqm truth table function symbol cke dqm n ? 1 n u l data write / output enable enb h l data mask / output disable mask h h upper byte write enable / output enable enbu h l lower byte write enable / output enable enbl h l upper byte write inhibit / output disable masku h h lower byte write inhibit / output disable maskl h h remark h = high level, l = low level, = high or low level (don't care) 4.3 cke truth table current state function symbol cke /cs /ras /cas /we address n ? 1 n activating clock suspend mode entry h l any clock suspend mode l l clock suspend clock suspend mode exit l h idle cbr (auto) refresh command ref h h l l l h idle self refresh entry self h l l l l h self refresh self refresh exit l h l h h h lhh idle power down entry h l power down power down exit l h remark h = high level, l = low level, = high or low level (don't care) 

data sheet e0122n10 16 pd4516421a, 4516821a, 4516161a for rev.p 4.4 operative command table note1 (1/3) current state /cs /ras /cas /we address command action notes idle h desl nop or power down 2 lhh nop or bst nop or power down 2 l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act row activating l l h l ba, a10 pre/pall nop lllh ref/self cbr (auto) refresh or self refresh 4 l l l l op-code mrs mode register accessing row active h desl nop lhh nop or bst nop l h l h ba, ca, a10 read/reada begin read : determine ap 5 l h l l ba, ca, a10 writ/writa begin write : determine ap 5 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall precharge 6 lllh ref/self illegal l l l l op-code mrs illegal read h desl continue burst to end row active lhhh nop continue burst to end row active lhhl bst burst stop row active l h l h ba, ca, a10 read/reada terminate burst, new read : determine ap 7 l h l l ba, ca, a10 writ/writa terminate burst, start write : determine ap 7, 8 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall terminate burst, precharging lllh ref/self illegal l l l l op-code mrs illegal write h desl continue burst to end write recovering lhhh nop continue burst to end write recovering lhhl bst burst stop row active l h l h ba, ca, a10 read/reada terminate burst, start read : determine ap 7, 8 l h l l ba, ca, a10 writ/writa terminate burst, new write : determine ap 7 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall terminate burst, precharging 9 lllh ref/self illegal l l l l op-code mrs illegal 

data sheet e0122n10 17 pd4516421a, 4516821a, 4516161a for rev.p (2/3) current state /cs /ras /cas /we address command action notes read with auto h desl continue burst to end precharging precharge l h h h nop continue burst to end precharging lhhl bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 lllh ref/self illegal llllop-code mrs illegal write with auto precharge h desl continue burst to end write recovering with auto precharge lhhh nop continue burst to end write recovering with auto precharge lhhl bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 lllh ref/self illegal llllop-code mrs illegal precharging h desl nop enter idle after t rp lhhh nop nop enter idle after t rp lhhl bst nop enter idle after t rp l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall nop enter idle after t rp lllh ref/self illegal llllop-code mrs illegal row activating h desl nop enter bank active after t rcd lhhh nop nop enter bank active after t rcd lhhl bst illegal l h l h ba, ca, a10 read/reada illegal 3 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3, 10 l l h l ba, a10 pre/pall illegal 3 lllh ref/self illegal llllop-code mrs illegal 

data sheet e0122n10 18 pd4516421a, 4516821a, 4516161a for rev.p (3/3) current state /cs /ras /cas /we address command action notes write recovering h desl nop enter row active after t dpl lhhh nop nop enter row active after t dpl lhhl bst nop enter row active after t dpl l h l h ba, ca, a10 read/reada start read, determine ap 8 l h l l ba, ca, a10 writ/writa new write, determine ap l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 lllh ref/self illegal llllop-code mrs illegal write recovering h desl nop enter precharge after t dpl with auto precharge l h h h nop nop enter precharge after t dpl lhhl bst nop enter precharge after t dpl l h l h ba, ca, a10 read/reada illegal 3, 8 l h l l ba, ca, a10 writ/writa illegal 3 l l h h ba, ra act illegal 3 l l h l ba, a10 pre/pall illegal 3 lllh ref/self illegal llllop-code mrs illegal refreshing h desl nop enter idle after t rc lhh nop/bst nop enter idle after t rc lhl read/writ illegal llh act/pre/pall illegal lll ref/self/mrs illegal mode register h desl nop enter idle after t rsc accessing l h h h nop nop enter idle after t rsc lhhl bst illegal lhl read/writ illegal ll act/pre/pall/ ref/self/mrs illegal notes 1. all entries assume that cke was active (high level) during the preceding clock cycle. 2. if both banks are idle, and cke is inactive (low level), pd4516 xxxa w ill enter power down mode. all input buffers except cke will be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. if both banks are idle, and cke is inactive (low level), pd4516 xxxa w ill enter self refresh mode. all input buffers except cke will be disabled. 5. illegal if t rcd is not satisfied. 6. illegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. must mask preceding data which don't satisfy t dpl . 10. illegal if t rrd is not satisfied. remark h = high level, l = low level, = high or low level (don?t care), v = valid data 

data sheet e0122n10 19 pd4516421a, 4516821a, 4516161a for rev.p 4.5 command truth table for cke current state cke /cs /ras /cas /we address action notes n ? 1 n self refresh h invalid, clk (n ? 1) would exit self refresh lhh self refresh recovery lhlhh self refresh recovery lhlhl illegal lhll illegal ll maintain self refresh self refresh recovery h h h idle after t rc hhlhh idle after t rc hhlhl illegal hhl l illegal hlh illegal hllhh illegal hllhl illegal hlll illegal power down h invalid, clk (n ? 1) would exit power down lh exit power down idle ll maintain power down mode both banks idle h h h refer to operations in operative command table hhlh refer to operations in operative command table hhl lh refer to operations in operative command table hhlllh cbr (auto) refresh h h l l l l op-code refer to operations in operative command table hlh refer to operations in operative command table hllh refer to operations in operative command table hlllh refer to operations in operative command table hllllh self refresh 1 hlllllop-coderefer to operations in operative command table l power down 1 row active h refer to operations in operative command table l power down 1 any state other than h h refer to operations in operative command table listed above h l begin clock suspend next cycle 2 lh exit clock suspend next cycle ll maintain clock suspend notes 1. self refresh can be entered only from the both banks idle state. power down can be entered only from both banks idle or row active state. 2. must be legal command as defined in operative command table. remark h = high level, l = low level, = high or low level (don't care) 

data sheet e0122n10 20 pd4516421a, 4516821a, 4516161a for rev.p 4.6 command truth table for two banks operation notes1,2 /cs /ras /cas /we ba a10 a9-a0 action from state note3 to state note4 h nop any any lhhh nop any any lhhl bst (r/w/a)0 (i/a)1 a0(i/a)1 i0 (i/a) i0(i/a)1 (r/w/a)1 (i/a)0 a1(i/a)0 i1 (i/a)0 i1(i/a)0 l h l h h h ca read (r/w/a)1 (i/a)0 rp1(i/a)0 h h ca a1(r/w)0 rp1a0 h l ca (r/w/a)1 (i/a)0 r1(i/a)0 h l ca a1(r/w)0 r1a0 l h ca (r/w/a)0 (i/a)1 rp0(i/a)1 l h ca a0(r/w)1 rp0a1 l l ca (r/w/a)0 (i/a)1 r0(i/a)1 l l ca a0(r/w)1 r0a1 l h l l h h ca write (r/w/a)1 (i/a)0 wp1(i/a)0 h h ca a1(r/w)0 wp1a0 h l ca (r/w/a)1 (i/a)0 w1(i/a)0 h l ca a1(r/w)0 w1a0 l h ca (r/w/a)0 (i/a)1 wp0(i/a)1 l h ca a0(r/w)1 wp0a1 l l ca (r/w/a)0 (i/a)1 w0(i/a)1 l l ca a0(r/w)1 w0a1 l l h h h ra activate row i1any0 a1any0 l ra i0any1 a0any1 llhl h precharge (r/w/a/i)0 (i/a)1 i0i1 h (r/w/a/i)1 (i/a)0 i1i0 hl (r/w/a/i)1 (i/a)0 i1(i/a)0 hl (i/a)1 (r/w/a/i)0 i1(r/w/a/i)0 ll (r/w/a/i)0 (i/a)1 i0(i/a)1 ll (i/a)0 (r/w/a/i)1 i0(r/w/a/i)1 lllh refresh i0i1 i0i1 l l l l op - code mode register access i0i1 i0i1 remark h = high level, l = low level, = high or low level (don't care) ba = bank address (a11) 

data sheet e0122n10 21 pd4516421a, 4516821a, 4516161a for rev.p notes 1. state abbreviations i = idle a = row active r = read with no precharge (no precharge is posted) w = write with no precharge (no precharge is posted) rp = read with auto precharge (precharge is posted) wp = write with auto precharge (precharge is posted) any = any state x0y1 = y1x0 = bank a is in state ?x?, bank b is in state ?y? (x/y)0z1 = z1(x/y)0 = bank a is in state ?x? or ?y?, bank b is in state ?z? 3. if the pd4516 xxxa is in a state other t han above listed in the ?from state? column, the command is illegal. 4. the states listed under ?to? might not be entered on the next clock cycle. timing restrictions apply. 

data sheet e0122n10 22 pd4516421a, 4516821a, 4516161a for rev.p 5. initialization the synchronous dram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 100 s or longer pause must precede any signal toggling. (2) after the pause, both banks must be precharged using the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum t rp is satisfied, the mode register can be programmed. after the mode register set cycle, t rsc (2 clk minimum) pause must be satisfied as well. (4) two or more cbr (auto) refresh must be performed. remarks 1. the sequence of mode register programming and refresh above may be transposed. 2. cke and dqm must be held high until the precharge command is issued to ensure data-bus hi-z. 

data sheet e0122n10 23 pd4516421a, 4516821a, 4516161a for rev.p 6. programming the mode register the mode register is programmed by the mode register set command using address bits a11 through a0 as data inputs. the register retains data until it is reprogrammed or the device loses power. the mode register has four fields; options : a11 through a7 /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clk have elapsed. /cas latency /cas latency is the most critical of the parameters being set. it tells the device how many clocks must elapse before the data will be available. the value is determined by the frequency of the clock and the speed grade of the device. 13.3 relationship between frequency and latency shows the relationship of /cas latency to the clock period and the speed grade of the device. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become hi-z. the burst length is programmable as 1, 2, 4, 8 or full page. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either ?sequential? or ?interleave?. the method chosen will depend on the type of cpu in the system. some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. 7.1 burst length and sequence shows the addressing sequence for each burst length using them. both sequences support bursts of 1, 2, 4 and 8. additionally, sequence supports the full page length. 

data sheet e0122n10 24 pd4516421a, 4516821a, 4516161a for rev.p 7. mode register wt = 1 1 2 4 8 r r r r 1 0 0 0 0 0 1 2 3 4 5 76 8 9 10 11 jedec standard test set (refresh counter test) bl wt ltmode 0 0 1 0 1 2 3 4 5 76 8 9 10 11 burst read and single write (for write through cache) 0 1 0 1 2 3 4 5 76 8 9 10 11 use in future v v v v v v 1v 1 0 1 2 3 4 5 76 8 9 10 11 vender specific bl wt ltmode 0 0 0 0 0 0 1 2 3 4 5 76 8 9 10 11 mode register set v = valid = don?t care wt = 0 1 2 4 8 r r r full page bits2-0 000 001 010 011 100 101 110 111 burst length sequential interleave 0 1 wrap type /cas latency r r 2 3 r r r r bits6-4 000 001 010 011 100 101 110 111 latency mode clk cke /cs /ras /cas /we a0 - a11 mode register write 

data sheet e0122n10 25 pd4516421a, 4516821a, 4516161a for rev.p 7.1 burst length and sequence [burst of two] starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00, 10, 1 11, 01, 0 [burst of four] starting address (column address a1 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [burst of eight] starting address (column address a2 - a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page burst is an extension of the above tables of sequential addressing, with the length being 512 (for 2m 8 device), 1,024 (for 4m 4 device), and 256 (for 1m 16 device). 

data sheet e0122n10 26 pd4516421a, 4516821a, 4516161a for rev.p 8. address bits of bank-select and precharge a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 row (activate command) select bank a ?activate? command 0 result precharge bank a precharge bank b precharge all banks a10 0 0 1 select bank b ?activate? command 1 a11 0 1 a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 (precharge command) disables auto-precharge (end of burst) 0 enables auto-precharge (end of burst) 1 enables read/write commands for bank a 0 enables read/write commands for bank b 1 a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 col. (/cas strobes) : don ? t care clk cke /cs /ras /cas /we h a10 a11 clk cke /cs /ras /cas /we h a10 a11 clk cke /cs /ras /cas /we h a10 a11 precharge for bank a precharge for bank b precharge for both banks 

data sheet e0122n10 27 pd4516421a, 4516821a, 4516161a for rev.p 9. precharge the precharge command can be issued anytime after t ras (min.) is satisfied. soon after the precharge command is issued, precharge operation performed and the synchronous dram enters the idle state after t rp is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. it is depending on the /cas latency and clock cycle time. t0 t1 t2 t3 t4 t5 t6 t7 burst length=4 read read q1 q2 q3 q4 pre hi-z q1 q2 q3 q4 pre hi-z (t ras must be satisfied) clk command /cas latency = 2 dq command /cas latency = 3 dq t8 in order to write all data to the memory cell correctly, the asynchronous parameter ?t dpl ? must be satisfied. the t dpl (min.) specification defines the earliest time that a precharge command can be issued. minimum number of clocks is calculated by dividing t dpl (min.) with clock cycle time. in summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. in the following table, minus means clocks before the reference; plus means time after the reference. /cas latency read write 2?1+t dpl (min.) 3?2+t dpl (min.) 

data sheet e0122n10 28 pd4516421a, 4516821a, 4516161a for rev.p 10. auto precharge during a read or write command cycle, a10 controls whether auto precharge is selected. a10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begins automatically. the t ras must be satisfied with a read with auto precharge or a write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. in read cycle, once auto precharge has started, an activate command to the bank can be issued after t rp has been satisfied. in write cycle, the t dal must be satisfied to issue the next activate command to the bank being precharged. the timing that begins the auto precharge cycle depends on both the /cas latency programmed into the mode register and whether read or write cycle. 10.1 read with auto precharge during a read cycle, the auto precharge begins one clock earlier (/cas latency of 2) or two clocks earlier (/cas latency of 3) the last data word output. qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras must be satisfied) t9 remark reada means read with auto precharge 

data sheet e0122n10 29 pd4516421a, 4516821a, 4516161a for rev.p 10.2 write with auto precharge during a write cycle, the auto precharge starts one clock after the last data word input to the device (/cas latency of 2 or 3). db1 db2 db3 db4 auto precharge starts writa b hi-z db1 db2 db3 db4 auto precharge starts writa b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras must be satisfied) remark writa means write with auto precharge in summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. in the table below, minus means clocks before the reference; plus means after the reference. /cas latency read write 2?1+1 3?2+1 

data sheet e0122n10 30 pd4516421a, 4516821a, 4516161a for rev.p 11. read / write command interval 11.1 read to read command interval during a read cycle, when new read command is issued, it will be effective after /cas latency, even if the previous read operation does not completed. read will be interrupted by another read. the interval between the commands is 1 cycle minimum. each read command can be issued in every clock without any restriction. qb1 qb2 qb3 qb4 hi-z read a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 read b qa1 1cycle t9 11.2 write to write command interval during a write cycle, when a new write command is issued, the previous burst will terminate and the new burst will begin with a new write command. write will be interrupted by another write. the interval between the commands is minimum 1 cycle. each write command can be issued in every clock without any restriction. db1 db2 db3 db4 hi-z write a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 write b da1 1cycle 

data sheet e0122n10 31 pd4516421a, 4516821a, 4516161a for rev.p 11.3 write to read command interval write command and read command interval is also 1 cycle. only the write data before read command will be written. the data bus must be hi-z at least one cycle prior to the first d out . qb1 qb2 qb3 qb4 write a hi-z qb1 qb2 qb3 qb4 write a hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 da1 da1 read b read b 

data sheet e0122n10 32 pd4516421a, 4516821a, 4516161a for rev.p 11.4 read to write command interval during a read cycle, read can be interrupted by write. the read and write command interval is 1 cycle minimum. there is a restriction to avoid data conflict. the data bus must be hi-z using dqm before write. d1 d2 d3 d4 read dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 write dqm hi-z 1cycle read can be interrupted by write. dqm must be high at least 3 clocks prior to the write command. clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 8 t9 q1 q2 q3 read dq command d1 d2 d3 write dqm hi-z is necessary q1 q2 read dq command d1 d2 d3 write dqm hi-z is necessary /cas latency = 2 /cas latency = 3 

data sheet e0122n10 33 pd4516421a, 4516821a, 4516161a for rev.p 12. burst termination there are two methods to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. 12.1 burst stop command during a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to hi-z after the /cas latency from the burst stop command. read command clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x q1 q2 q3 dq /cas latency = 2 hi-z q1 q2 q3 dq /cas latency = 3 hi-z bst remark bst: burst stop command during a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to hi-z at the same clock with the burst stop command. d2 d3 d4 write dq command /cas latency = 2, 3 clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x bst hi-z d1 remark bst: burst stop command 

data sheet e0122n10 34 pd4516421a, 4516821a, 4516161a for rev.p 12.2 precharge termination 12.2.1 precharge termination in read cycle during a read cycle, the burst read operation is terminated by a precharge command. when the precharge command is issued, the burst read operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. to issue a precharge command, t ras must be satisfied. when /cas latency is 2, the read data will remain valid until one clock after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 q1 dq command q2 q3 q4 act t rp pre hi-z (t ras must be satisfied) when /cas latency is 3, the read data will remain valid until two clocks after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command q1 q2 q3 act t rp pre hi-z t8 q4 (t ras must be satisfied) 

data sheet e0122n10 35 pd4516421a, 4516821a, 4516161a for rev.p 12.2.2 precharge termination in write cycle during a write cycle, the burst write operation is terminated by a precharge command. when the precharge command is issued, the burst write operation is terminated and precharge starts. the same bank can be activated again after t rp from the precharge command. to issue a precharge command, t ras must be satisfied. when /cas latency is 2, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. write clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 dq command d1 d2 d3 act dqm t rp pre hi-z d4 d5 (t ras must be satisfied) when /cas latency is 3, the write data written prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. write clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command d1 d2 d3 act dqm t rp pre hi-z d5 t8 d4 (t ras must be satisfied) 

data sheet e0122n10 36 pd4516421a, 4516821a, 4516161a for rev.p 13. electrical specifications ? all voltages are referenced to v ss (gnd). ? after power up, wait more than 100 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc , v cc q ? 0.5 to +4.6 v voltage on any pin relative to gnd v t ? 0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 1w operating ambient temperature t a 0 to 70 c storage temperature t stg ? 55 to + 125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc , v cc q 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc +0.3 note1 v low level input voltage v il ? 0.3 note2 +0.8 v operating ambient temperature t a 070 c notes 1. v ih (max.) = v cc + 2.0 v (pulse width 3 ns) 2. v il (min.) = ?2.0 v (pulse width 3 ns) pin capacitance (t a = 25 c, f = 1 mhz) parameter symbol condition min. typ. max. unit input capacitance c i1 a0 - a11 2.5 4 pf c i2 clk, cke, /cs, /ras, /cas, /we, dqm, udqm, ldqm 2.5 4 data input / output capacitance c i/o dq0 - dq15 4 6 pf 

data sheet e0122n10 37 pd4516421a, 4516821a, 4516161a for rev.p dc characteristics 1 (recommended operating conditions unless otherwise noted) parameter symbol test condition /cas grade maximum unit notes latency 4 8 16 operating current i cc1 burst length = 1, cl = 2 -80 100 105 110 ma 1 t rc t rc (min.) , io = 0 ma, -10 100 105 110 one bank active -10b 85 90 95 -12859095 cl = 3 -80 110 115 120 -10 110 115 120 -10b 90 95 100 -12 90 95 100 precharge standby current i cc2 pcke v il (max.) , t ck = 15 ns 3 3 3 ma in power down mode i cc2 ps cke v il (max.) , t ck = 222 precharge standby current i cc2 ncke v ih (min.) , t ck = 15 ns, /cs v ih (min.) , 252525ma in non power down mode i nput signals are changed one time during 30 ns. i cc2 ns cke v ih (min.) , t ck = , 666 input signals are stable. active standby current i cc3 pcke v il (max.) , t ck = 15 ns 3 3 3 ma in power down mode i cc3 ps cke v il (max.) , t ck = 222 active standby current in non power down mode i cc3 ncke v ih (min.) , t ck = 15 ns, /cs v ih (min.) , input signals are changed one time during 30 ns. 28 28 30 ma i cc3 ns cke v ih (min.) , t ck = , 121215 input signals are stable. operating current i cc4 t ck t ck (min.) , io = 0 ma, cl = 2 -80 95 105 110 ma 2 (burst mode) both banks active -10 75 85 90 -10b 75 85 90 -12657580 cl = 3 -80 110 120 125 -10 90 100 105 -10b 90 100 105 -12809095 cbr (auto) refresh current i cc5 t rc = 100 ns, cl = 2 -80 90 90 90 ma 3 t ck = min. -10909090 -10b 90 90 90 -12909090 cl = 3 -80 90 90 90 -10909090 -10b 90 90 90 -12909090 self refresh current i cc6 cke 0.2 v -** 1 1 1 ma -**l 250 250 250 a 

data sheet e0122n10 38 pd4516421a, 4516821a, 4516161a for rev.p notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured condition that addresses are changed only one time during t ck (min.) . 2. i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck (min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck (min.) . dc characteristics 2 (recommended operating conditions unless otherwise noted) parameter symbol test condition min. typ. max. unit note input leakage current i i (l) 0 v i v cc q, v cc q = v cc ? 1.0 +1.0 a all other pins not under test = 0 v output leakage current i o (l) 0 v o v cc q, d out is disabled ? 1.5 +1.5 a high level output voltage v oh i o = ? 4 ma 2.4 v low level output voltage v ol i o = +4 ma 0.4 v 

data sheet e0122n10 39 pd4516421a, 4516821a, 4516161a for rev.p ac characteristics (recommended operating conditions unless otherwise noted) test conditions parameter value unit ac high level input voltage / low level input voltage 2.0 / 0.8 v input timing measurement reference level 1.4 v transition time (input rise and fall time) 1 ns output timing measurement reference level 1.4 v t ck t ch t cl 2.0 v 1.4 v 0.8 v clk 2.0 v 1.4 v 0.8 v input t setup t hold output t ac t oh 

data sheet e0122n10 40 pd4516421a, 4516821a, 4516161a for rev.p synchronous characteristics parameter symbol -80 - 10 -10b - 12 unit note min. max. min. max. min. max. min. max. clock cycle time /cas latency = 3 t ck3 8 (125 mhz) 10 (100 mhz) 10 (100 mhz) 12 (83 mhz) ns /cas latency = 2 t ck2 10 (100 mhz) 13 (77 mhz) 13 (77 mhz) 15 (67 mhz) ns access time from clk /cas latency = 3 t ac3 6678ns1 /cas latency = 2 t ac2 6888ns1 clk high level width t ch 3 3 3.5 4 ns clk low level width t cl 3 3 3.5 4 ns data-out hold time t oh 3333ns1 data-out low-impedance time t lz 0000ns data-out high-impedance time /cas latency = 3 t hz3 36363738ns /cas latency = 2 t hz2 36383838ns data-in setup time t ds 2 2 2.5 3 ns data-in hold time t dh 1111.5ns address setup time t as 2 2 2.5 3 ns address hold time t ah 1111.5ns cke setup time t cks 2 2 2.5 3 ns cke hold time t ckh 1111.5ns cke setup time (power down exit) t cksp 2 2 2.5 3 ns command (/cs, /ras, /cas, /we, dqm) setup time t cms 2 2 2.5 3 ns command (/cs, /ras, /cas, /we, dqm) hold time t cmh 1111.5ns note 1. output load output z = 50 ? 1.4 v 50 pf 50 ? 

data sheet e0122n10 41 pd4516421a, 4516821a, 4516161a for rev.p asynchronous characteristics parameter symbol -80 - 10 -10b - 12 unit note min. max. min. max. min. max. min. max. ref to ref/act command period t rc 70 70 90 90 ns act to pre command period t ras 48 120,000 50 120,000 60 120,000 60 120,000 ns pre to act command period t rp 20 20 26 30 ns delay time act to read/write command t rcd 20 20 26 30 ns act (one) to act (another) command period t rrd 16 20 20 24 ns data-in to pre command period t dpl 8101012ns data-in to act (ref) command period /cas latency = 3 t dal3 1clk +20 1clk +20 1clk +26 1clk +30 ns (auto precharge) /cas latency = 2 t dal2 1clk +20 1clk +20 1clk +26 1clk +30 ns mode register set cycle time t rsc 2222clk transition time t t 0.5 30 1 30 1 30 1 30 ns refresh time -** t ref 32 32 32 32 ms (2,048 refresh cycles) -**l 64 64 64 64 

data sheet e0122n10 42 pd4516421a, 4516821a, 4516161a for rev.p clk cke /cs /ras /cas /we a11 a10 add dqm dq t ac t lz t ac t oh t hz t oh t cks t ch t cl t ck t rcd t ras t rrd t rc t rp hi-z l t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t cms t cmh t as t ah t ckh bank a activate command bank a read command bank a precharge command bank b activate command bank b read command with auto precharge bank a activate command auto precharge start for bank b 13.1 ac parameters for read timing (burst length = 2, /cas latency = 2) 

data sheet e0122n10 43 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq t cks t cms t ckh t as t ah l hi-z t ds t dh t rcd t rrd t dal t rc t dpl t rp bank a activate command bank a precharge command bank a write command without auto precharge bank a activate command bank b write command with auto precharge bank b activate command bank a write command with auto precharge bank a activate command auto precharge start for bank a auto precharge start for bank b t cmh 13.2 ac parameters for write timing (burst length = 4, /cas latency = 3) 

data sheet e0122n10 44 pd4516421a, 4516821a, 4516161a for rev.p 13.3 relationship between frequency and latency speed version -80 -10 -10b -12 clock cycle time [ns] 8 10 10 13 10 13 12 15 frequency [mhz] 125 100 100 77 100 77 83 67 /cas latency 32323232 [t rcd ] 32223232 /ras latency (/cas latency + [t rcd ]) 64546464 [t rc ] 97769786 [t ras ] 65546554 [t rrd ] 22222222 [t rp ] 32223232 [t dpl ] 11111111 [t dal ] 43334343 [t rsc ] 22222222 

data sheet e0122n10 45 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq all banks precharge command t rp register write command activate command is valid hi-z h address key t rsc 2clk (min.) 13.4 mode register set (burst length = 4, /cas latency = 2) 

data sheet e0122n10 46 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq cke all banks precharge command is necessary t rp t rc t rc register write command is necessary refresh command is necessary refresh command is necessary activate command hi-z high level is necessary high level is necessary address key t rsc 2 refresh cycles are necessary clock signal is necessary 13.5 power on sequence and cbr (auto) refresh 

data sheet e0122n10 47 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h dab1 dab2 dab3 dab4 qaa1 qaa2 qaa3 qaa4 raa raa caa cab l activate command for bank a read command for bank a write command for bank a precharge command for bank a l 13.6 /cs function (at 100 mhz, burst length = 4, /cas latency = 3) only /cs signal needs to be issued at minimum rate 

data sheet e0122n10 48 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq l raa raa caa qaa1 qaa2 qaa3 qaa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at end of burst read command for bank a 13.7 clock suspension during burst read (using cke function) (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 49 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq l raa raa caa qaa1 qaa2 qaa3 qaa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at end of burst read command for bank a clock suspension during burst read (using cke function) (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 50 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq l raa raa caa daa1 daa2 daa3 daa4 activate command for bank a 1-clock suspended 2-clock suspended write command for bank a 3-clock suspended 13.8 clock suspension during burst write (using cke function) (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 51 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq l raa raa caa activate command for bank a write command for bank a daa1 daa2 daa3 daa4 1-clock suspended 2-clock suspended 3-clock suspended clock suspension during burst write (using cke function) (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 52 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq l raa caa activate command for bank a precharge command qaa1 qaa2 qaa4 clock mask start clock mask end qaa3 power down mode entry power down mode exit precharge standby read command for bank a power down mode exit power down mode entry active standby t cksp t cksp valid raa 13.9 power down mode and clock mask (burst length = 4, /cas latency = 2) 

data sheet e0122n10 53 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk /cs /ras /cas /we a11 a10 add dq cke dom dqm l precharge command if necessary cbr refresh cbr refresh activate command read command q1 t rp t rc t rc h 13.10 cbr (auto) refresh 

data sheet e0122n10 54 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t7 t8 t9 t10 t11 t12 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dom dq dqm l precharge command if necessary self refresh entry t rp self refresh exit self refresh entry or (activate command) next clock enable self refresh exit next clock enable activate command t rc t rc 13.11 self refresh (entry and exit) 

data sheet e0122n10 55 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h l raa caa cac rad cad raa rad cab l qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 activate command for bank a read command for bank a read command for bank a precharge command for bank a activate command for bank a read command for bank a qad1 qad2 qad3 read command for bank a 13.12 random column read (page with same bank) (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 56 pd4516421a, 4516821a, 4516161a for rev.p raa t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq l qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 raa caa cab cac raa caa raa h activate command for bank a read command for bank a read command for bank a read command for bank a precharge command for bank a activate command for bank a read command for bank a random column read (page with same bank) (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 57 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h dba1 dba2 dba3 dba4 dbb1 dbb2 dbc1 dbc2 dbc3 dbc4 activate command for bank b dbd1 dbd2 dbd3 dbd4 l rba cba rba cbb cbc rbd cbd write command for bank b write command for bank b precharge command for bank b write command for bank b rbd activate command for bank b write command for bank b 13.13 random column write (page with same bank) (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 58 pd4516421a, 4516821a, 4516161a for rev.p rba t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq l dba1 dba2 dba3 dba4 dbb1 dbb2 dbc1 dbc2 dbc3 dbc4 rba cba cbb cbc rbd cbd rbd h activate command for bank b write command for bank b write command for bank b write command for bank b precharge command for bank b activate command for bank b write command for bankb dbd1 dbd2 random column write (page with same bank) (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 59 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 qaa8 rba cba rba raa caa rbb cbb raa rbb l activate command for bank b t rcd read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b t rp 13.14 random row read (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) 

data sheet e0122n10 60 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dom dq h dqm l dq qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 rba cba raa caa rbb cbb rba raa rbb activate command for bank b read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b precharge command for bank a t rcd t rp random row read (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) 

data sheet e0122n10 61 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h daa1 daa2 daa3 daa4 daa5 daa6 daa7 daa8 dba1 dba2 dba3 dba4 dba5 dba6 dba7 dab1 raa caa raa rba cba rab cab rba rab l activate command for bank a t rcd write command for bank a activate command for bank b write command for bank b precharge command for bank a activate command for bank a write command for bank a t rp dba8 dab2 dab3 precharge command for bank b t dpl t dpl 13.15 random row write (ping-pong banks) (1/2) (burst length = 8, /cas latency = 2) 

data sheet e0122n10 62 pd4516421a, 4516821a, 4516161a for rev.p t0 clk cke /cs /ras /cas /we a11 a10 add dqm dq activate command for bank a write command for bank a activate command for bank b write command for bank b t rcd h l activate command for bank a t dpl t dpl daa1 daa2 daa3 daa4 daa5 daa6 daa7 daa8 dba1 dba2 dba3 dba4 dba5 dba6 dba7 dba8 dab1 dab2 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 precharge command for bank a write command for bank a precharge command for bank b t rp raa raa caa rba rba cba rab rab cab random row write (ping-pong banks) (2/2) (burst length = 8, /cas latency = 3) 

data sheet e0122n10 63 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h raa caa cab cac raa activate command for bank a read command for bank a hi-z at the end of wrap function write command for bank a qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab4 qac1 qac2 qac4 0-clock latency read command for bank a 2-clock latency hi-z write latency = 0 word masking 13.16 read and write (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 64 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h raa caa cab cac raa activate command for bank a read command for bank a hi-z at the end of wrap function write command for bank a qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab4 qac1 qac2 0-clock latency read command for bank a 2-clock latency hi-z write latency = 0 word masking read and write (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 65 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq activate command for bank a ba1 ba2 bc1 bc2 bd1 bd2 bd3 bd4 aa1 aa2 aa3 aa4 bb1 bb2 ab1 ab2 raa caa rba cba cbb cbc cab cbd raa rba h l activate command for bank b read command for bank a read command for bank b read command for bank b read command for bank b read command for bank a read command for bank b precharge command for bank a precharge command for bank b t rrd t rcd 13.17 interleaved column read cycle (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 66 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq add raa rba raa rba caa cab cbb cbc cba ba1 ba2 bc1 bc2 aa1 aa2 aa3 aa4 bb1 bb2 ab1 ab2 ab3 ab4 activate command for bank a activate command for bank b read command for bank a read command for bank b read command for bank b read command for bank b read command for bank a precharge command for bank b precharge command for bank a t rrd t rcd h l interleaved column read cycle (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 67 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq activate command for bank a ba1 ba2 bc1 bc2 bd1 bd2 bd3 bd4 aa1 aa2 aa3 aa4 bb1 bb2 ab1 ab2 raa caa rba cba cbb cbc cab cbd raa rba h l activate command for bank b write command for bank a write command for bank b write command for bank b write command for bank b write command for bank a write command for bank b precharge command for bank a precharge command for bank b t rrd t rcd t dpl t dpl 13.18 interleaved column write cycle (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 68 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq activate command for bank a ba1 ba2 bc1 bc2 bd1 bd2 bd3 bd4 aa1 aa2 aa3 aa4 bb1 bb2 ab1 ab2 activate command for bank b write command for bank a write command for bank b write command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b t rrd t rcd h l raa rba cbc cbd raa rba caa cba cab cbb write command for bank b t dpl t dpl interleaved column write cycle (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 69 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h raa caa cab cbb rac cac raa rba rbb rac rba cba rbb hi-z activate command for bank a activate command for bank b bank a read command without auto precharge bank b read command with auto precharge bank a read command with auto precharge activate command for bank b auto precharge start for bank b auto precharge start for bank a bank b read command with auto precharge activate command for bank a auto precharge start for bank b bank a read command with auto precharge l 13.19 auto precharge after read burst (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 70 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h l hi-z activate command for bank a auto precharge start for bank b activate command for bank b bank a read command without auto precharge bank b read command with auto precharge bank a read command with auto precharge activate command for bank b auto precharge start for bank a bank b read command with auto precharge raa rba raa caa rba cba cab rbb cbb rbb auto precharge after read burst (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 71 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq raa caa cab cbb rac cac raa rba rbb rac rba cba rbb hi-z activate command for bank a activate command for bank b bank a write command without auto precharge bank b write command with auto precharge bank a write command with auto precharge activate command for bank b auto precharge start for bank b activate command for bank a l h bank b write command with auto precharge auto precharge start for bank a bank a write command with auto precharge auto precharge start for bank b 13.20 auto precharge after write burst (1/2) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 72 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h l hi-z raa rba raa caa rba cba cab rbb cbb rbb activate command for bank a activate command for bank b bank a write command without auto precharge bank b write command with auto precharge bank a write command with auto precharge auto precharge start for bank b activate command for bank b auto precharge start for bank a bank b write command with auto precharge auto precharge after write burst (2/2) (burst length = 4, /cas latency = 3) 

data sheet e0122n10 73 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h raa rba raa caa rba cba rbb rbb l hi-z read command for bank a read command for bank b precharge command for bank b activate command for bank b burst stop command activate command for bank a activate command for bank b aa aa+1 aa+2 aa ? 2aa ? 1 aa aa+1 ba ba+1 ba+2 ba+3 ba+6 ba+5 ba+4 13.21 full page read cycle (1/2) (/cas latency = 2) 

data sheet e0122n10 74 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h raa rba raa caa rba cba rbb rbb l hi-z read command for bank a read command for bank b activate command for bank b burst stop command activate command for bank a activate command for bank b aa aa+1 aa ? 3aa ? 2aa ? 1 aa aa+1 ba ba+1 ba+2 ba+3 ba+5 ba+4 precharge command for bank b full page read cycle (2/2) (/cas latency = 3) 

data sheet e0122n10 75 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h aa aa+1 aa+2 aa ? 2 aa ? 1 aa aa+1 ba ba+1 ba+2 ba+3 ba+4 ba+5 raa rba raa caa rba cba rbb rbb l hi-z write command for bank a write command for bank b precharge command for bank b activate command for bank b burst stop command activate command for bank a activate command for bank b 13.22 full page write cycle (1/2) (/cas latency = 2) 

data sheet e0122n10 76 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h aa aa+1 aa+2 aa+3 aa ? 1 aa aa+1 ba ba+1 ba+2 ba+3 ba+4 raa rba raa caa rba cba rbb rbb l hi-z write command for bank a write command for bank b precharge command for bank b activate command for bank b burst stop command activate command for bank a activate command for bank b full page write cycle (2/2) (/cas latency = 3) 

data sheet e0122n10 77 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add ldqm udqm dq lower dq upper h activate command read command u-byte not read l-byte not write u-byte not write l-byte not write l-byte not read l-byte not read l-byte not read 13.23 byte write operation (burst length = 4, /cas latency = 2) 

data sheet e0122n10 78 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add ldqm udqm dq lower dq upper h activate command read command single write command single write command read command single write command 13.24 burst read and single write (option) (burst length = 4, /cas latency = 2) 

data sheet e0122n10 79 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq h qaa1 qba1 qab1 qab2 qbb1 qbb2 qac1 qac2 qac3 qbc1 qbc2 qbc3 raa rba raa rba caa cba cab cbb cac cbc activate command for bank a activate command for bank b read command for bank a read command for bank b read command for bank a read command for bank b read command for bank a read command for bank b precharge command for bank b (pre termination) t rcd t rrd t rcd l hi-z 13.25 full page random column read (burst length = full page, /cas latency = 2) 

data sheet e0122n10 80 pd4516421a, 4516821a, 4516161a for rev.p t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke /cs /ras /cas /we a11 a10 add dqm dq l daa1 dba1 dab1 dab2 dbb1 dbb2 dac1 dac2 dac3 dbc1 dbc2 dbc3 write command for bank a dbc4 activate command for bank a activate command for bank b write command for bank b write command for bank a write command for bank b write command for bank a write command for bank b precharge command for bank b (pre termination) raa rba raa rba caa cba cab cbb cac cbc t rcd t rrd t rcd h 13.26 full page random column write (burst length = full page, /cas latency = 2) 

data sheet e0122n10 81 pd4516421a, 4516821a, 4516161a for rev.p raa raa rab rab cab caa t0 clk cke /cs /ras /cas /we a11 a10 add dqm dq activate command for bank a write command for bank a activate command for bank a read command for bank a t rcd h l t ras daa1 daa2 daa3 daa4 daa5 qab1 qab2 qab3 qab4 qab5 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 pre command termination precharge command for bank a pre command termination precharge command for bank a write masking t ras t dpl t rp hi-z 13.27 pre (precharge) termination of burst (1/2) (burst length = 8, /cas latency = 2) 

data sheet e0122n10 82 pd4516421a, 4516821a, 4516161a for rev.p raa raa rab rab cab caa t0 clk cke /cs /ras /cas /we a11 a10 add dqm dq activate command for bank a write command for bank a activate command for bank a t rcd h l t ras daa1 daa2 daa3 daa4 daa5 qab1 qab2 qab3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 pre command termination bank a precharge command write masking t ras t dpl t rp hi-z read command for bank a pre command termination bank a precharge command qab4 pre (precharge) termination of burst (2/2) (burst length = 8, /cas latency = 3) 

data sheet e0122n10 83 pd4516421a, 4516821a, 4516161a for rev.p 14. package drawings 44-pin plastic tsop( ii ) (10.16 mm (400)) notes 1. each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2. dimension "a" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. item millimeters a c 18.32 + ? + ? + ? s44g5-80-9nf-1 44 23 122 s c m l u t s q r d m s n g b detail of lead end k j h i a ? ? 

data sheet e0122n10 84 pd4516421a, 4516821a, 4516161a for rev.p 1. each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. ? 2. dimension ? a ? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 50-pin plastic tsop( ii ) (10.16 mm (400)) notes item millimeters a c 20.86 0.04 1.0 max. g b 0.8 (t.p.) 1.0 0.05 h 11.76 0.2 i 10.11 0.04 j 0.825 0.2 m 0.13 l 0.5 q 0.1 0.05 n 0.10 k 0.145 + 0.025 ? 0.015 t 0.25 (t.p.) s 1.2 max. u 0.60 0.15 r d 0.32 + 0.08 ? 0.07 3 + 5 ? 3 s50g5-80-9nf-1 k c s g q r l t dm b j detail of lead end s n m 50 26 125 u s a ? 2 h i 

data sheet e0122n10 85 pd4516421a, 4516821a, 4516161a for rev.p 15. recommended soldering condition please consult with our sales offices for soldering conditions of the pd4516 xxxa. type of surface mount device pd4516421ag5-9nf : 44-pin plastic tsop (ii) (10.16mm (400)) pd4516821ag5-9nf : 44-pin plastic tsop (ii) (10.16mm (400)) pd4516161ag5-9nf : 50-pin plastic tsop (ii) (10.16mm (400)) 

data sheet e0122n10 86 pd4516421a, 4516821a, 4516161a for rev.p 16. revision history edition / page description date this edition previous edition type of revision location nec corporation (m12939e) 3rd edition / apr. 1998 ?? ? ? elpida memory, inc. (e0122n) 1st edition / may. 2001 ? ? ? republished by elpida memory, inc. 

data sheet e0122n10 87 pd4516421a, 4516821a, 4516161a for rev.p notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 

pd4516421a, 4516821a, 4516161a for rev.p m02 01. 2 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. 


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